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Yeun Ho Joung (PhD student)

 

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Biographical Sketch

Yeun. H Joung received the B.S. and M.S.E.E. degree from Sung-Kyun-Kwan University, Seoul, Korea in 1995 and 1997, respectively and is currently pursuing the Ph.D. degree in electrical and computer engineering at Georgia Institute of Technology, Atlanta.

 

Home: 404-634-2541

Office: 404-894-9909

Fax: 404-894-5025

gt7432d@mail.gatech.edu

jhaseung@bellsouth.net

 

Projects:

 

1.        Integral microsystem with electroplating bonding technology (Jun. 2002 ~ Jun.2003)

-          Design and fabrication of platinum microheater.

-          Design and fabrication of S-shape flexible chip interconnect.

-         Integration Electroplating bonded flexible chip interconnect with microsystem.

 2.        Electroplating bonded solenoid inductor.  (Jun. 2001 ~ Jun. 2002)

-          High Q-factor electroplating bonded RF inductor design and fabrication with plated-through-mold.

-          High Q-factor electroplating bonded RF inductor design and fabrication with polymer-core method.

3.        Electroplating bonding technology (Nov. 1999~May. 2001)

-          Development of electroplating bonding technology for chip interconnects method.

-          Fabrication and design of 256 electroplating bonded chip interconnect system.

-          Thermal ANYS simulation of the electroplating bonded system.

4.        Flexible wafer level packaging  (Jan. 1999 ~ Oct. 1999)

-          Design and fabrication of  flexible wafer level packaing

 

Publications:

 

·         Yeun-Ho Joung and Mark G. Allen, High Density Electroplating Bonding Interconnect Technology: Chip Packaging and High Aspect Ratio Passive Elements”, Proc 53rd Electronic Components and Technology Conf, New Orleans, LA, 2003, pp.640 -646

·        Yeun-Ho Joung, et al, “Integrated Inductors in the Chip-to-Board Interconnect Layer Fabricated Using Solderless Electroplating Bonding”, 2002 IEEE MTT-S International Microwave Symposium Digest, May 2002, pp.1409-1412( Student paper contest finalist)

·        Yeun-Ho Joung and Mark G. Allen, “Micromachined Flexible Interconnect for Wafer Level Packaging”, Proceedings of 2001 ASME, November 11-16, 2001, New York, NY

·        US Patent-pending, Yeun-Ho Joung and Mark G. Allen,  “Method of Electroplating Bonding”

·        Chirag S. Patel, Yeun-Ho Joung, Kevin P. Martin, and James D. Meindl, " Reliability and Thermo-Mechanical Analysis of Compliant Wafer Level Package", 3th Annual Semiconductor Packaging Symposium, SEMICON West, July 11-12, San Jose, CA 2000

·        Yeun-Ho Joung and Jun-Tae Song, "Fabrication of SAW Filter Using PZT Ceramics", Journal of KIEEME Vol.10, No.1, pp.1-pp.7 (1997.1)

·        Yeun-Ho Joung, Dong-Hun Yeo, and Jun-Tae Song, "Fabrication of SAW Filter on PZT and LiNbO3 Substrates", Proceeding of the Autumn Symposium of KIEEME, pp.40-43 (1996.11)

·        Master Thesis: Yeun-Ho Joung, “A Study of Properties and Fabrication of SAW Filters on PZT AND LiNbO3 Substrates,” 1995

 

 

 

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